At frequencies of 200 MHz, digital frequency dividers become difficult to implement. Presently, the fastest commercially available logic family, commonly known as MECL III, has a worst case setup time of approximately 0.5 nsec per flip-flop, a worst case delay time of approximately 2.9 nsec per flip-flop, and a worst case delay time of approximately 1.0 nsec per gate. At 200 MHz a signal period is approximately 4.5 nsec; thus to allow real time processing of an applied signal, any feedback control requiring a response time within a signal period must have a critical timing path of less than 4.5 nsec.